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tda7293 120v - 100w dmos audio amplifier with mute/st-by very high operating voltage range ( 50v) dmos power stage high output power (100w @ thd = 10%, r l = 8 w , v s = 40v) muting/stand-by functions no switch on/off noise very low distortion very low noise short circuit protected (with no in- put signal applied) thermal shutdown clip detector modularity (more devices can be easily connected in parallel to drive very low impedances) description the tda7293 is a monolithic integrated circuit in multiwatt15 package, intended for use as audio class ab amplifier in hi-fi field applications (home stereo, self powered loudspeakers, top- class tv). thanks to the wide voltage range and to the high out current capability it is able to sup- ply the highest power into both 4 w and 8 w loads. the built in muting function with turn on delay simplifies the remote operation avoiding switching on-off noises. parallel mode is made possible by connecting more device through of pin11. high output power can be delivered to very low impedance loads, so optimizing the thermal dissipation of the system. january 2003 ? in- 2 r2 680 w c2 22 m f c1 470nf in+ r1 22k 3 r3 22k - + mute stby 4 vmute vstby 10 9 sgnd mute stby r4 22k thermal shutdown s/c protection r5 10k c3 10 m f c4 10 m f 1 stby-gnd c5 22 m f 713 14 6 15 8 -vs -pwvs bootstrap out +pwvs +vs c9 100nf c8 1000 m f -vs d97au805a +vs c7 100nf c6 1000 m f buffer driver 11 boot loader 12 5 vclip clip det (*) (*) see application note (**) for slave function (**) figure 1: typical application and test circuit multiwatt15v multiwatt15h ordering numbers: tda7293v TDA7293HS multipower bcd technology 1/15
absolute maximum ratings symbol parameter value unit v s supply voltage (no signal) 60 v v 1 v stand-by gnd voltage referred to -v s (pin 8) 90 v v 2 input voltage (inverting) referred to -v s 90 v v 2 - v 3 maximum differential inputs 30 v v 3 input voltage (non inverting) referred to -v s 90 v v 4 signal gnd voltage referred to -v s 90 v v 5 clip detector voltage referred to -v s 120 v v 6 bootstrap voltage referred to -v s 120 v v 9 stand-by voltage referred to -v s 120 v v 10 mute voltage referred to -v s 120 v v 11 buffer voltage referred to -v s 120 v v 12 bootstrap loader voltage referred to -v s 100 v i o output peak current 10 a p tot power dissipation t case = 70 c50w t op operating ambient temperature range 0 to 70 c t stg , t j storage and junction temperature 150 c 1 2 3 4 5 6 7 9 10 11 8 buffer driver mute stand-by -v s (signal) +v s (signal) bootstrap clip and short circuit detector signal ground non inverting input inverting input stand-by gnd tab connected to pin 8 13 14 15 12 -v s (power) out +v s (power) bootstrap loader d97au806 pin connection (top view) thermal data symbol description typ max unit r th j-case thermal resistance junction-case 1 1.5 c/w tda7293 2/15
electrical characteristics (refer to the test circuit v s = 40v, r l = 8 w , r g = 50 w ; t amb = 25c, f = 1 khz; unless otherwise specified). symbol parameter test condition min. typ. max. unit v s supply range 12 50 v i q quiescent current 50 100 ma i b input bias current 0.3 1 m a v os input offset voltage -10 10 mv i os input offset current 0.2 m a p o rms continuous output power d = 1%: r l = 4 w; v s = 29v, 75 80 80 w d = 10% r l = 4 w ; v s = 29v 90 100 100 w d total harmonic distortion (**) p o = 5w; f = 1khz p o = 0.1 to 50w; f = 20hz to 15khz 0.005 0.1 % % i sc current limiter threshold v s 40v 6.5 a sr slew rate 5 10 v/ m s g v open loop voltage gain 80 db g v closed loop voltage gain (1) 29 30 31 db e n total input noise a = curve f = 20hz to 20khz 1 310 m v m v r i input resistance 100 k w svr supply voltage rejection f = 100hz; v ripple = 0.5vrms 75 db t s thermal protection device muted 150 c device shut down 160 c stand-by function (ref: to pin 1) v st on stand-by on threshold 1.5 v v st off stand-by off threshold 3.5 v att st-by stand-by attenuation 70 90 db i q st-by quiescent current @ stand-by 0.5 1 ma mute function (ref: to pin 1) v mon mute on threshold 1.5 v v moff mute off threshold 3.5 v att mute mute attenuation 60 80 db clip detector duty duty cycle ( pin 5) thd = 1% ; rl = 10k w to 5v 10 % thd = 10% ; rl = 10k w to 5v 30 40 50 % i cleak po = 50w 3 m a slave function pin 4 (ref: to pin 8 -v s ) v slave slavethreshold 1v v master master threshold 3 v note (1): g vmin 3 26db note: pin 11 only for modular connection. max external load 1m w /10 pf, only for test purpose note (**): tested with optimized application board (see fig. 2) tda7293 3/15
figure 2: typical application p.c. board and component layout (scale 1:1) tda7293 4/15
application suggestions (see test and application circuits of the fig. 1) the recommended values of the external components are those shown on the application circuit of fig- ure 1. different values can be used; the following table can help the designer. components suggested value purpose larger than suggested smaller than suggested r1 (*) 22k input resistance increase input impedance decrease input impedance r2 680 w closed loop gain set to 30db (**) decrease of gain increase of gain r3 (*) 22k increase of gain decrease of gain r4 22k st-by time constant larger st-by on/off time smaller st-by on/off time; pop noise r5 10k mute time constant larger mute on/off time smaller mute on/off time c1 0.47 m f input dc decoupling higher low frequency cutoff c2 22 m f feedback dc decoupling higher low frequency cutoff c3 10 m f mute time constant larger mute on/off time smaller mute on/off time c4 10 m f st-by time constant larger st-by on/off time smaller st-by on/off time; pop noise c5 22 m fxn (***) bootstrapping signal degradation at low frequency c6, c8 1000 m f supply voltage bypass c7, c9 0.1 m f supply voltage bypass danger of oscillation (*) r1 = r3 for pop optimization (**) closed loop gain has to be 3 26db (***) multiplay this value for the number of modular part connected master undefined slave -v s +3v -v s +1v -v s d98au821 slave function: pin 4 (ref to pin 8 -v s ) note: if in the application, the speakers are connected via long wires, it is a good rule to add between the output and gnd, a boucherot cell, in order to avoid dangerous spurious oscillations when the speakers terminal are shorted. the suggested boucherot resistor is 3.9 w /2w and the capacitor is 1 m f. tda7293 5/15
introduction in consumer electronics, an increasing demand has arisen for very high power monolithic audio amplifiers able to match, with a low cost, the per- formance obtained from the best discrete de- signs. the task of realizing this linear integrated circuit in conventional bipolar technology is made ex- tremely difficult by the occurence of 2nd break- down phoenomenon. it limits the safe operating area (soa) of the power devices, and, as a con- sequence, the maximum attainable output power, especially in presence of highly reactive loads. moreover, full exploitation of the soa translates into a substantial increase in circuit and layout complexity due to the need of sophisticated pro- tection circuits. to overcome these substantial drawbacks, the use of power mos devices, which are immune from secondary breakdown is highly desirable. the device described has therefore been devel- oped in a mixed bipolar-mos high voltage tech- nology called bcdii 100/120. 1) output stage the main design task in developping a power op- erational amplifier, independently of the technol- ogy used, is that of realization of the output stage. the solution shown as a principle shematic by fig3 represents the dmos unity - gain output buffer of the tda7293. this large-signal, high-power buffer must be ca- pable of handling extremely high current and volt- age levels while maintaining acceptably low har- monic distortion and good behaviour over frequency response; moreover, an accurate con- trol of quiescent current is required. a local linearizing feedback, provided by differen- tial amplifier a, is used to fullfil the above require- ments, allowing a simple and effective quiescent current setting. proper biasing of the power output transistors alone is however not enough to guarantee the ab- sence of crossover distortion. while a linearization of the dc transfer charac- teristic of the stage is obtained, the dynamic be- haviour of the system must be taken into account. a significant aid in keeping the distortion contrib- uted by the final stage as low as possible is pro- vided by the compensation scheme, which ex- ploits the direct connection of the miller capacitor at the amplifiers output to introduce a local ac feedback path enclosing the output stage itself. 2) protections in designing a power ic, particular attention must be reserved to the circuits devoted to protection of the device from short circuit or overload condi- tions. due to the absence of the 2nd breakdown phe- nomenon, the soa of the power dmos transis- tors is delimited only by a maximum dissipation curve dependent on the duration of the applied stimulus. in order to fully exploit the capabilities of the power transistors, the protection scheme imple- mented in this device combines a conventional soa protection circuit with a novel local tempera- ture sensing technique which " dynamically" con- trols the maximum dissipation. figure 3: principle schematic of a dmos unity-gain buffer. tda7293 6/15
in addition to the overload protection described above, the device features a thermal shutdown circuit which initially puts the device into a muting state (@ tj = 150 o c) and then into stand-by (@ tj = 160 o c). full protection against electrostatic discharges on every pin is included. 3) other features the device is provided with both stand-by and mute functions, independently driven by two cmos logic compatible input pins. the circuits dedicated to the switching on and off of the amplifier have been carefully optimized to avoid any kind of uncontrolled audible transient at the output. the sequence that we recommend during the on/off transients is shown by figure 4. the application of figure 5 shows the possibility of using only one command for both st-by and mute functions. on both the pins, the maximum appli- cable range corresponds to the operating supply voltage. application information high-efficiency constraints of implementing high power solutions are the power dissipation and the size of the power supply. these are both due to the low effi- ciency of conventional ab class amplifier ap- proaches. here below (figure 6) is described a circuit pro- posal for a high efficiency amplifier which can be adopted for both hi-fi and car-radio applica- tions. 1n4148 10k 30k 20k 10 m f 10 m f mute stby d93au014 mute/ st-by figure 5: single signal st-by/mute control circuit play off st-by mute mute st-by off d98au817 5v 5v +vs (v) +40 -40 v mute pin #10 (v) v st-by pin #9 (v) -vs v in (mv) i q (ma) v out (v) figure 4: turn on/off suggested sequence tda7293 7/15
the tda7293 is a monolithic mos power ampli- fier which can be operated at 100v supply voltage (120v with no signal applied) while delivering out- put currents up to 6.5 a. this allows the use of this device as a very high power amplifier (up to 180w as peak power with t.h.d.=10 % and rl = 4 ohm); the only drawback is the power dissipation, hardly manageable in the above power range. the typical junction-to-case thermal resistance of the tda7293 is 1 o c/w (max= 1.5 o c/w). to avoid that, in worst case conditions, the chip tem- perature exceedes 150 o c, the thermal resistance of the heatsink must be 0.038 o c/w (@ max am- bient temperature of 50 o c). as the above value is pratically unreachable; a high efficiency system is needed in those cases where the continuous rms output power is higher than 50-60 w. the tda7293 was designed to work also in higher efficiency way. for this reason there are four power supply pins: two intended for the signal part and two for the power part. t1 and t2 are two power transistors that only operate when the output power reaches a certain threshold (e.g. 20 w). if the output power in- creases, these transistors are switched on during the portion of the signal where more output volt- age swing is needed, thus "bootstrapping" the power supply pins (#13 and #15). the current generators formed by t4, t7, zener diodes z1, z2 and resistors r7,r8 define the minimum drop across the power mos transistors of the tda7293. l1, l2, l3 and the snubbers c9, r1 and c10, r2 stabilize the loops formed by the "bootstrap" circuits and the output stage of the tda7293. by considering again a maximum average output power (music signal) of 20w, in case of the high efficiency application, the thermal resistance value needed from the heatsink is 2.2 o c/w (vs = 50 v and rl= 8 ohm). all components (tda7293 and power transis- tors t1 and t2) can be placed on a 1.5 o c/w heatsink, with the power darlingtons electrically insulated from the heatsink. since the total power dissipation is less than that of a usual class ab amplifier, additional cost sav- ings can be obtained while optimizing the power supply, even with a high heatsink . bridge application another application suggestion is the bridge configuration, where two tda7293 are used. in this application, the value of the load must not be lower than 8 ohm for dissipation and current capability reasons. a suitable field of application includes hi-fi/tv subwoofers realizations. the main advantages offered by this solution are: - high power performances with limited supply voltage level. - considerably high output power even with high load values (i.e. 16 ohm). with rl= 8 ohm, vs = 25v the maximum output power obtainable is 150 w, while with rl=16 ohm, vs = 40v the maximum pout is 200 w. application note: (ref. fig. 7) modular application (more devices in parallel) the use of the modular application lets very high power be delivered to very low impedance loads. the modular application implies one device to act as a master and the others as slaves. the slave power stages are driven by the master device and work in parallel all together, while the in- put and the gain stages of the slave device are dis- abled, the figure below shows the connections re- quired to configure two devices to work together. the master chip connections are the same as the normal single ones. the outputs can be connected together with- out the need of any ballast resistance. the slave sgnd pin must be tied to the nega- tive supply. the slave st-by and mute pins must be con- nected to the master st-by and mute pins. the bootstrap lines must be connected to- gether and the bootstrap capacitor must be in- creased: for n devices the boostrap capacitor must be 22 m f times n. the slave in-pin must be connected to the negative supply. the bootstrap capacitor for compatibility purpose with the previous de- vices of the family, the boostrap capacitor can be connected both between the bootstrap pin (6) and the output pin (14) or between the boostrap pin (6) and the bootstrap loader pin (12). when the bootcap is connected between pin 6 and 14, the maximum supply voltage in presence of output signal is limited to 100v, due the boot- strap capacitor overvoltage. when the bootcap is connected between pins 6 and 12 the maximum supply voltage extend to the full voltage that the technology can stand: 120v. this is accomplished by the clamp introduced at the bootstrap loader pin (12): this pin follows the output voltage up to 100v and remains clamped at 100v for higher output voltages. this feature lets the output voltage swing up to a gate-source voltage from the positive supply (v s -3 to 6v). tda7293 8/15
tda7293 3 1 4 13 7 815 2 14 6 10 r3 680 c11 22 m f l3 5 m h r18 270 r16 13k c15 22 m f 9 r12 13k c13 10 m f r13 20k c12 330nf r15 10k c14 10 m f r14 30k d5 1n4148 play st-by r17 270 l1 1 m h t1 bdx53a t3 bc394 d3 1n4148 r4 270 r5 270 t4 bc393 t5 bc393 r6 20k r7 3.3k c16 1.8nf r8 3.3k c17 1.8nf z2 3.9v z1 3.9v l2 1 m h r19 270 d4 1n4148 d2 byw98100 r1 2 r2 2 c9 330nf c10 330nf t2 bdx54a t6 bc393 t7 bc394 t8 bc394 r9 270 r10 270 r11 20k out in c7 100nf c5 1000 m f 35v c8 100nf c6 1000 m f 35v c1 1000 m f 63v c2 1000 m f 63v c3 100nf c4 100nf +50v +25v d1 byw98100 gnd -25v -50v d97au807c 12 d6 1n4001 r20 20k r21 20k d7 1n4001 r22 10k r23 10k p ot figure 6: high efficiency application circuit figure 6a: pcb and component layout of the fig. 6 tda7293 9/15
in- 2 r2 680 w c2 22 m f c1 470nf in+ r1 22k 3 r3 22k - + mute stby 4 10 9 sgnd mute stby r4 22k thermal shutdown s/c protection r5 10k c3 10 m f c4 10 m f 1 stby-gnd c5 47 m f 713 14 6 15 8 -vs -pwvs bootstrap out +pwvs +vs c9 100nf c8 1000 m f -vs d97au808d +vs c7 100nf c6 1000 m f buffer driver 11 boot loader 12 in- 2 in+ 3 - + mute stby 4 10 9 sgnd mute thermal shutdown s/c protection 1 stby-gnd 713 14 6 15 8 -vs -pwvs bootstrap out +pwvs +vs c9 100nf c8 1000 m f -vs +vs c7 100nf c6 1000 m f buffer driver 11 boot loader 12 5 clip det 5 master slave c10 100nf r7 2 w vmute vstby stby figure 7: modular application circuit figure 6b: pcb - solder side of the fig. 6. tda7293 10/15
figure 8b: modular application p.c. board and component layout (scale 1:1) (solder side) figure 8a: modular application p.c. board and component layout (scale 1:1) (component side) tda7293 11/15
0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 2100 51020 50 vs = +/-29v rl = 4 ohm f = 1khz f = 20 khz pout (w) t.h.d (%) figure 9: distortion vs output power 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 t.h.d (%) 2 100 51020 50 vs = +/-40v rl = 8 ohm f = 1khz f = 20 khz pout (w) figure 10: distortion vs output power 20 25 30 35 40 45 50 supply voltage (+/-vcc) 0 10 20 30 40 50 60 pdissipated (w) dissipated power for each device of the modular application 4ohm 8ohm pd limit at tcase=70c figure 13: modular application pd vs vsupply (ref. fig. 7) 20 25 30 35 40 45 50 supply voltage (+/-vcc) 0 1 2 3 4 5 6 minimum allovable load (ohm) forbidden area pd > 50w at t case =70c figure 12: modular application derating rload vs vsupply (ref. fig. 7) 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 vs (+/-v) 0 10 20 30 40 50 60 70 80 90 100 110 120 po (w) thd=0.5 % rl=8 ohm f= 1 khz t.h.d.=10 % figure 14: output power vs. supply voltage 00.11 10100 frequency (khz) 0.001 0.01 0.1 1 10 t.h.d. (%) vs= +/- 35 v rl= 8 ohm pout=100 mw po=50 w figure 11: distortion vs frequency tda7293 12/15
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dim. mm inch min. typ. max. min. typ. max. a 5 0.197 b 2.65 0.104 c 1.6 0.063 e 0.49 0.55 0.019 0.022 f 0.66 0.75 0.026 0.030 g 1.14 1.27 1.4 0.045 0.050 0.055 g1 17.57 17.78 17.91 0.692 0.700 0.705 h1 19.6 0.772 h2 20.2 0.795 l 20.57 0.810 l1 18.03 0.710 l2 2.54 0.100 l3 17.25 17.5 17.75 0.679 0.689 0.699 l4 10.3 10.7 10.9 0.406 0.421 0.429 l5 5.28 0.208 l6 2.38 0.094 l7 2.65 2.9 0.104 0.114 s 1.9 2.6 0.075 0.102 s1 1.9 2.6 0.075 0.102 dia1 3.65 3.85 0.144 0.152 multiwatt15 h outline and mechanical data tda7293 14/15
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com tda7293 15/15

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